Continuing advances in the semiconductor industry have made possible the production of integrated circuits with increasingly larger numbers of logic or other elements on a single chip. The increasing complexity of application specific integrated circuits ("ASIC's") made possible by these advances and the high costs involved in initial production of a chip from a logic design have made logic simulation an important step in the chip design process. Logic simulation techniques are available in the art for simulating operation of a logic design for a chip prior to the start of fabrication of the chip, to uncover any operational errors therein, and to permit redesign as necessary before committing the design to chip fabrication. Various logic simulation computer programs are known in the art for performing this function. In addition, hardware logic simulators such as that disclosed in U.S. Pat. No. 4,769,817 issued on Sep. 6, 1988, provide highly efficient techniques for simulating and testing logic device designs.
A problem existing in the semiconductor industry is in the testing of manufactured chips. Even assuming a good, error-free logic design, it is well known that various faults and errors can enter into the production process which can result in functional defects in a manufactured chip. These faults can enter through a variety of causes in the numerous manufacturing process steps, and can affect any of the different gates, switches or lines on the chip. Although the causes of such errors are diverse, as a practical matter for testing purposes, they can be considered to occur on essentially a random basis anywhere in a chip. This presents a problem for production testing of chips, since for complex chips such as microprocessors or other integrated circuits there are so many circuit elements and combinations of inputs and outputs that it becomes impractical to test all possible input combinations against the known design standard to determine if a fault exists and to isolate the fault, if existing.
One current technique for determining if an application specific integrated circuit is faulty is to use a commercial integrated circuit tester to apply test vectors to a physical device and compare the resultant output of the device with simulated data representative of the flawless design of this same circuit. Using this technique, a faulty chip can be detected. However, the exact fault cannot be diagnosed without further testing of the integrated circuit.
Typically, a hardware fault simulator is used to determine if a given set of test vectors may be used to test for a defective chip. The hardware fault simulator is also used to simulate data output, or "signature", representative of a flawless integrated circuit which is compared to the actual physical test data, or "signature", of the integrated circuit to determine if a defect in the integrated circuit design exists. However, once a chip, or its design, has been tested as defective, it is difficult to determine the particular fault therein.
It is, therefore, desirable to develop a technique diagnosing faults in chips which locates the actual defect present within a defective integrated circuit design. It is also desirable to develop such a technique for diagnosing faults in an application specific integrated circuit which is capable of diagnosing such faults in circuits designed without the use of level sensitive scan design techniques.